School of Information Sciences, Manipal

  • India

Research Output 1990 2019

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Conference contribution
2018

Design and Analysis of Booth Multiplier with Optimised Power Delay Product

Chaitanya, C. V. S. & Kumar, P., 20-08-2018, 2018 International Conference on Computer Communication and Informatics, ICCCI 2018. Institute of Electrical and Electronics Engineers Inc., 8441236. (2018 International Conference on Computer Communication and Informatics, ICCCI 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
multipliers
products
Electric power utilization
Networks (circuits)
2015

High level modeling of physical layer noise parameters using SystemC

Lohani, P. K., Ranjani, K., Shankar, R. R., Sundaresan, C. & Chaitanya, C. V. S., 09-01-2015, 2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014. Institute of Electrical and Electronics Engineers Inc., Vol. 2014-August. p. 344-347 4 p. 7006275

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Hardware
Communication
Industry
Modeling
Leverage
2014

Experimental evaluation of PID and ESO controller for instrument landing system

Jain, R. K., Shetty, P. K. & Shenoy, S., 01-01-2014, 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies, ICCICCT 2014. Institute of Electrical and Electronics Engineers Inc., p. 751-757 7 p. 6993059

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Derivatives
Controllers
Aircraft models
Landing
Computer simulation
2013

Implementation of HDLC controller design using Verilog HDL

Nagpurwala, A. H., Sundaresan, C. & Chaitanya, C. V. S., 01-01-2013, 2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013. Institute of Electrical and Electronics Engineers Inc., p. 7-10 4 p. 6895033

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Computer hardware description languages
Controllers
Network protocols
OSI model
Data communication systems

Novel method of digital clock frequency multiplication and division using floating point arithmetic

Chidambaram, S. & Chaitanya, V. S., 20-05-2013, Proceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013. p. 592-595 4 p. 6498340

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Digital arithmetic
Floating-point Arithmetic
Clocks
Division
Multiplication
2011
4 Citations (Scopus)

Floating gate Wilson current mirror for low power applications

Madhushankara, M. & Shetty, P. K., 20-07-2011, Trends in Networks and Communications - International Conferences, NeCoM, WeST, WiMoN 2011, Proceedings. p. 500-507 8 p. (Communications in Computer and Information Science; vol. 197 CCIS).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Energy dissipation
Mirror
Mirrors
MOSFET
Networks (circuits)
6 Citations (Scopus)

Modified reduced delay BCD adder

Sundaresan, C., Chaitanya, C. V. S., Venkateswaran, P. R., Bhat, S. & Kumar, J. M., 2011, Proceedings - 2011 4th International Conference on Biomedical Engineering and Informatics, BMEI 2011. Vol. 4. p. 2148-2151 4 p. 6098679

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Adders
Processing
Industry
2008
4 Citations (Scopus)

Color image analysis to grade shades of a color and its application to quantify stained tissues

Prasad, K. & Nayak, P. K., 01-12-2008, 4th Kuala Lumpur International Conference on Biomedical Engineering 2008, Biomed 2008. 1 ed. Vol. 21 IFMBE. p. 154-157 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Color image processing
Tissue
Color
Coloring Agents
Tumors