A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology

V. K. Joshi, S. Borkar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and PP-SRAM cells with 6T SRAM cell in hold mode by 60.09% and 0.22% at temperature (T) = 25°C, 63.25% and 3.34% at T = 50°C, 63.82% and 3.37% at T = 100°C respectively. For our transistors sizing we obtain a degradation in write operation of NC-SRAM cell by 7.31% compare to 6T SRAM cell, While it is unchanged in case of PP-SRAM cell. Significant reduction in total leakage power is obtained for NC and PP-SRAM cells compared to 6T SRAM cell by 77.06% and 47.42% at T = 25°C, 76.89% and 48.98% at T = 50°C, 76.87% and 50.94% at T = 100°C respectively, which is due to the gate and sub-threshold leakage currents. We also design a 16 bit memory array of 6T, NC and PP SRAM cells. There is a reduction in total leakage power for 16 bit array of NC and PP-SRAM cells by 69.86 %, 50.75 % respectively compared to the 16 bit array of 6T SRAM cell. All the simulations are performed by Cadence Virtuoso (version IC 6.1.6.500.1) tool using gpdk 45nm CMOS process technology.

Original languageEnglish
Title of host publication2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages58-62
Number of pages5
ISBN (Electronic)9781509028894
DOIs
Publication statusPublished - 27-03-2017
Event2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 - Putrajaya, Malaysia
Duration: 14-11-201616-11-2016

Conference

Conference2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
CountryMalaysia
CityPutrajaya
Period14-11-1616-11-16

Fingerprint

Static random access storage
random access memory
CMOS
Transistors
transistors
Data storage equipment
cells
Leakage currents
leakage
Degradation
sizing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Biomedical Engineering
  • Control and Systems Engineering
  • Hardware and Architecture
  • Computer Networks and Communications
  • Instrumentation

Cite this

Joshi, V. K., & Borkar, S. (2017). A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 (pp. 58-62). [7888009] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICAEES.2016.7888009
Joshi, V. K. ; Borkar, S. / A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology. 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 58-62
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title = "A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology",
abstract = "Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and PP-SRAM cells with 6T SRAM cell in hold mode by 60.09{\%} and 0.22{\%} at temperature (T) = 25°C, 63.25{\%} and 3.34{\%} at T = 50°C, 63.82{\%} and 3.37{\%} at T = 100°C respectively. For our transistors sizing we obtain a degradation in write operation of NC-SRAM cell by 7.31{\%} compare to 6T SRAM cell, While it is unchanged in case of PP-SRAM cell. Significant reduction in total leakage power is obtained for NC and PP-SRAM cells compared to 6T SRAM cell by 77.06{\%} and 47.42{\%} at T = 25°C, 76.89{\%} and 48.98{\%} at T = 50°C, 76.87{\%} and 50.94{\%} at T = 100°C respectively, which is due to the gate and sub-threshold leakage currents. We also design a 16 bit memory array of 6T, NC and PP SRAM cells. There is a reduction in total leakage power for 16 bit array of NC and PP-SRAM cells by 69.86 {\%}, 50.75 {\%} respectively compared to the 16 bit array of 6T SRAM cell. All the simulations are performed by Cadence Virtuoso (version IC 6.1.6.500.1) tool using gpdk 45nm CMOS process technology.",
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Joshi, VK & Borkar, S 2017, A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology. in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016., 7888009, Institute of Electrical and Electronics Engineers Inc., pp. 58-62, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016, Putrajaya, Malaysia, 14-11-16. https://doi.org/10.1109/ICAEES.2016.7888009

A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology. / Joshi, V. K.; Borkar, S.

2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 58-62 7888009.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and PP-SRAM cells with 6T SRAM cell in hold mode by 60.09% and 0.22% at temperature (T) = 25°C, 63.25% and 3.34% at T = 50°C, 63.82% and 3.37% at T = 100°C respectively. For our transistors sizing we obtain a degradation in write operation of NC-SRAM cell by 7.31% compare to 6T SRAM cell, While it is unchanged in case of PP-SRAM cell. Significant reduction in total leakage power is obtained for NC and PP-SRAM cells compared to 6T SRAM cell by 77.06% and 47.42% at T = 25°C, 76.89% and 48.98% at T = 50°C, 76.87% and 50.94% at T = 100°C respectively, which is due to the gate and sub-threshold leakage currents. We also design a 16 bit memory array of 6T, NC and PP SRAM cells. There is a reduction in total leakage power for 16 bit array of NC and PP-SRAM cells by 69.86 %, 50.75 % respectively compared to the 16 bit array of 6T SRAM cell. All the simulations are performed by Cadence Virtuoso (version IC 6.1.6.500.1) tool using gpdk 45nm CMOS process technology.

AB - Data stability, performance and leakage currents are the few important issues of Static Random Access Memory (SRAM) due to scaling down the technology. We revisited these issues by making a comparative study of N-Controlled SRAM cell (NC-SRAM) and PMOS pass transistor SRAM cell (PP-SRAM) with conventional 6T SRAM cell. We observe decrease in Static Noise Margin (SNM) of NC-SRAM and PP-SRAM cells with 6T SRAM cell in hold mode by 60.09% and 0.22% at temperature (T) = 25°C, 63.25% and 3.34% at T = 50°C, 63.82% and 3.37% at T = 100°C respectively. For our transistors sizing we obtain a degradation in write operation of NC-SRAM cell by 7.31% compare to 6T SRAM cell, While it is unchanged in case of PP-SRAM cell. Significant reduction in total leakage power is obtained for NC and PP-SRAM cells compared to 6T SRAM cell by 77.06% and 47.42% at T = 25°C, 76.89% and 48.98% at T = 50°C, 76.87% and 50.94% at T = 100°C respectively, which is due to the gate and sub-threshold leakage currents. We also design a 16 bit memory array of 6T, NC and PP SRAM cells. There is a reduction in total leakage power for 16 bit array of NC and PP-SRAM cells by 69.86 %, 50.75 % respectively compared to the 16 bit array of 6T SRAM cell. All the simulations are performed by Cadence Virtuoso (version IC 6.1.6.500.1) tool using gpdk 45nm CMOS process technology.

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Joshi VK, Borkar S. A comparative study of NC and PP-SRAM cells with 6T SRAM cell using 45nm CMOS technology. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 58-62. 7888009 https://doi.org/10.1109/ICAEES.2016.7888009