TY - JOUR
T1 - A novel self write-terminated driver for hybrid STT-MTJ/CMOS LIM structure
AU - Barla, Prashanth
AU - Joshi, Vinod Kumar
AU - Bhat, Somashekara
N1 - Publisher Copyright:
© 2020 THE AUTHORS
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2021/6/1
Y1 - 2021/6/1
N2 - A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure. Using continuous write monitoring mechanism, the novel circuitry completely eliminates the unnecessary flow of write current which abolishes the wastage of write energy in the proposed write driver. Hence, the total energy required for writing process is reduced noticeably by 63.32% in novel write driver compared to the conventional write circuit. Monte-Carlo simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ. Simulations are also carried out for the proposed write driver, by varying the transistor sizes and supply voltage to analyze its switching probability to obtain safe operating region. Further, the proposed write driver is integrated with hybrid full adder to demonstrate its feasibility in low-power VLSI circuits.
AB - A novel self write-terminated driver is proposed for the hybrid spin transfer torque-magnetic tunnel junction (STT-MTJ)/CMOS circuits based on logic-in-memory (LIM) structure. Using continuous write monitoring mechanism, the novel circuitry completely eliminates the unnecessary flow of write current which abolishes the wastage of write energy in the proposed write driver. Hence, the total energy required for writing process is reduced noticeably by 63.32% in novel write driver compared to the conventional write circuit. Monte-Carlo simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ. Simulations are also carried out for the proposed write driver, by varying the transistor sizes and supply voltage to analyze its switching probability to obtain safe operating region. Further, the proposed write driver is integrated with hybrid full adder to demonstrate its feasibility in low-power VLSI circuits.
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U2 - 10.1016/j.asej.2020.10.012
DO - 10.1016/j.asej.2020.10.012
M3 - Article
AN - SCOPUS:85097735998
SN - 2090-4479
JO - Ain Shams Engineering Journal
JF - Ain Shams Engineering Journal
ER -