A Tutorial on Design of Datapath and Controller of an ALU using Verilog and Verification using Open Source EDA Tools

In this paper, the method of designing datapath and controller of an ALU using verilog hardware description language is illustrated with help of an example. Initially, the architecture of ALU at functional blocks level is laid out, so that datapath can be designed based on that. Later, the algorithmic flow chart and synchronous sequential state diagram for controller is drawn. A verilog code for the ALU which consists of above two sub-modules is written. Open source tool called iverilog is utilized for simulating the verilog code. It dumps the result on a file from which timing diagram of various signals can be plotted. Another open source software called Gtkwave is used for this purpose. So, in this paper, starting from systematic design of ALU, coding in verilog to simulation and verification using free tools is explained.