An Efficient Architecture for Modified Lifting-Based Discrete Wavelet Transform

Rohan Pinto, Kumara Shama

Research output: Contribution to journalArticlepeer-review

Abstract

A high speed and memory efficient lifting based architecture for one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is proposed in this paper. The lifting algorithm is modified in this work to achieve a critical path of one multiplier delay with minimum pipeline registers. A 1-D DWT structure with two-input/two-output and four-input/four-output is developed based on the modified lifting scheme. The proposed 2-D DWT architecture for the Daubechies 5/3 and 9/7 filter comprises of two 1-D processors, together with a transpose and a temporal memory. An efficient transpose block is presented, which utilizes three registers to transpose the output sequence of the 1-D DWT block. The transpose block is independent of the size of the image read for the transform. The scanning process of an N× N image for a one-level 2-D transform is in Z fashion to minimize the temporal buffer to 4N and 2N for the 9/7 and 5/3 mode DWT respectively. The comparison results show that the proposed structure is hardware cost-effective and memory efficient, which is favorable for real-time visual operations. The model is described in VHDL and synthesized using the Cadence tool in 90 nm technology.

Original languageEnglish
Article number53
JournalSensing and Imaging
Volume21
Issue number1
DOIs
Publication statusPublished - 01-12-2020

All Science Journal Classification (ASJC) codes

  • Instrumentation
  • Electrical and Electronic Engineering

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