An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits

Subir Kumar Sarkar, Ankush Ghosh, M. A. Gautham, A. SobhaRani, Debasis Samanta

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Recently power dissipation (in addition to the earlier three aspects e.g. speed, size and cost) has become the main design concern in several applications. However, power saving should be achieved without compromising high performance or minimum area, thereby creating a new design culture for VLSI. Power consideration has been the ultimate design criteria in some special portable applications like pacemakers, mobile sets and wristwatches. As an attempt towards this, in the present work parallel back propagation artificial neural networks are employed to optimize and predict the various system parameter of a (In, Ga)As nanodevice so that the relevant device will exhibit better high frequency response and will be power efficient. Moreover prediction time is reduced using parallelism in ANN thereby making the design less time consuming.

Original languageEnglish
Title of host publicationProceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD
Pages232-235
Number of pages4
DOIs
Publication statusPublished - 01-12-2007
Externally publishedYes
Event14th International Workshop on the Physics of Semiconductor Devices, IWPSD - Mumbai, India
Duration: 16-12-200720-12-2007

Conference

Conference14th International Workshop on the Physics of Semiconductor Devices, IWPSD
CountryIndia
CityMumbai
Period16-12-0720-12-07

Fingerprint

VLSI circuits
Neural networks
Pacemakers
Backpropagation
Frequency response
Energy dissipation
Costs

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Sarkar, S. K., Ghosh, A., Gautham, M. A., SobhaRani, A., & Samanta, D. (2007). An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits. In Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD (pp. 232-235). [4472490] https://doi.org/10.1109/IWPSD.2007.4472490
Sarkar, Subir Kumar ; Ghosh, Ankush ; Gautham, M. A. ; SobhaRani, A. ; Samanta, Debasis. / An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits. Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD. 2007. pp. 232-235
@inproceedings{dce03329ff9a4be4a2e37c9adf626515,
title = "An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits",
abstract = "Recently power dissipation (in addition to the earlier three aspects e.g. speed, size and cost) has become the main design concern in several applications. However, power saving should be achieved without compromising high performance or minimum area, thereby creating a new design culture for VLSI. Power consideration has been the ultimate design criteria in some special portable applications like pacemakers, mobile sets and wristwatches. As an attempt towards this, in the present work parallel back propagation artificial neural networks are employed to optimize and predict the various system parameter of a (In, Ga)As nanodevice so that the relevant device will exhibit better high frequency response and will be power efficient. Moreover prediction time is reduced using parallelism in ANN thereby making the design less time consuming.",
author = "Sarkar, {Subir Kumar} and Ankush Ghosh and Gautham, {M. A.} and A. SobhaRani and Debasis Samanta",
year = "2007",
month = "12",
day = "1",
doi = "10.1109/IWPSD.2007.4472490",
language = "English",
isbn = "9781424417285",
pages = "232--235",
booktitle = "Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD",

}

Sarkar, SK, Ghosh, A, Gautham, MA, SobhaRani, A & Samanta, D 2007, An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits. in Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD., 4472490, pp. 232-235, 14th International Workshop on the Physics of Semiconductor Devices, IWPSD, Mumbai, India, 16-12-07. https://doi.org/10.1109/IWPSD.2007.4472490

An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits. / Sarkar, Subir Kumar; Ghosh, Ankush; Gautham, M. A.; SobhaRani, A.; Samanta, Debasis.

Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD. 2007. p. 232-235 4472490.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits

AU - Sarkar, Subir Kumar

AU - Ghosh, Ankush

AU - Gautham, M. A.

AU - SobhaRani, A.

AU - Samanta, Debasis

PY - 2007/12/1

Y1 - 2007/12/1

N2 - Recently power dissipation (in addition to the earlier three aspects e.g. speed, size and cost) has become the main design concern in several applications. However, power saving should be achieved without compromising high performance or minimum area, thereby creating a new design culture for VLSI. Power consideration has been the ultimate design criteria in some special portable applications like pacemakers, mobile sets and wristwatches. As an attempt towards this, in the present work parallel back propagation artificial neural networks are employed to optimize and predict the various system parameter of a (In, Ga)As nanodevice so that the relevant device will exhibit better high frequency response and will be power efficient. Moreover prediction time is reduced using parallelism in ANN thereby making the design less time consuming.

AB - Recently power dissipation (in addition to the earlier three aspects e.g. speed, size and cost) has become the main design concern in several applications. However, power saving should be achieved without compromising high performance or minimum area, thereby creating a new design culture for VLSI. Power consideration has been the ultimate design criteria in some special portable applications like pacemakers, mobile sets and wristwatches. As an attempt towards this, in the present work parallel back propagation artificial neural networks are employed to optimize and predict the various system parameter of a (In, Ga)As nanodevice so that the relevant device will exhibit better high frequency response and will be power efficient. Moreover prediction time is reduced using parallelism in ANN thereby making the design less time consuming.

UR - http://www.scopus.com/inward/record.url?scp=49749151015&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=49749151015&partnerID=8YFLogxK

U2 - 10.1109/IWPSD.2007.4472490

DO - 10.1109/IWPSD.2007.4472490

M3 - Conference contribution

AN - SCOPUS:49749151015

SN - 9781424417285

SP - 232

EP - 235

BT - Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD

ER -

Sarkar SK, Ghosh A, Gautham MA, SobhaRani A, Samanta D. An efficient technique of integrating parallel neural networks for faster and power efficient nanodevices for ultradense VLSI circuits. In Proceedings of the 14th International Workshop on the Physics of Semiconductor Devices, IWPSD. 2007. p. 232-235. 4472490 https://doi.org/10.1109/IWPSD.2007.4472490