ASIC implementation of DDR SDRAM memory controller

Amit Bakshi, Sudhanshu Shekhar Pandey, Tribikram Pradhan, Ratnadip Dey

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A Dedicated Memory Controller is of prime importance in applications that do not contain microprocessors (high-end applications). The Memory Controller provides command signals for memory refresh, read and write operation and initialization of SDRAM. Our work will focus on ASIC Design methodology of Double Data Rate (DDR) SDRAM Controller that is located between the DDR SDRAM and Bus Master. The Controller simplifies the SDRAM command interface to standard system read/write interface and also optimizes the access time of read/write cycle. Double Data Rate (DDR) SDRAM Controller is implemented using Cadence RTL Compiler.

Original languageEnglish
Title of host publication2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013
Pages74-78
Number of pages5
DOIs
Publication statusPublished - 2013
Event2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013 - Tirunelveli, India
Duration: 25-03-201326-03-2013

Conference

Conference2013 IEEE International Conference on Emerging Trends in Computing, Communication and Nanotechnology, ICE-CCN 2013
CountryIndia
CityTirunelveli
Period25-03-1326-03-13

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications

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