Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology

Vinod Kumar Joshi, Haniel Craig Lobo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.

Original languageEnglish
Title of host publicationAdvanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015
PublisherSpringer Verlag
Pages25-40
Number of pages16
Volume452
ISBN (Print)9789811010217
DOIs
Publication statusPublished - 2016
Event9th International Conference on Advanced Computing and Communication Technologies, ICACCT 2015 - New Delhi, India
Duration: 28-11-201529-11-2015

Publication series

NameAdvances in Intelligent Systems and Computing
Volume452
ISSN (Print)2194-5357

Conference

Conference9th International Conference on Advanced Computing and Communication Technologies, ICACCT 2015
CountryIndia
CityNew Delhi
Period28-11-1529-11-15

Fingerprint

Static random access storage
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Computer Science(all)

Cite this

Joshi, V. K., & Lobo, H. C. (2016). Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology. In Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015 (Vol. 452, pp. 25-40). (Advances in Intelligent Systems and Computing; Vol. 452). Springer Verlag. https://doi.org/10.1007/978-981-10-1023-1_3
Joshi, Vinod Kumar ; Lobo, Haniel Craig. / Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology. Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015. Vol. 452 Springer Verlag, 2016. pp. 25-40 (Advances in Intelligent Systems and Computing).
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abstract = "Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.",
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Joshi, VK & Lobo, HC 2016, Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology. in Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015. vol. 452, Advances in Intelligent Systems and Computing, vol. 452, Springer Verlag, pp. 25-40, 9th International Conference on Advanced Computing and Communication Technologies, ICACCT 2015, New Delhi, India, 28-11-15. https://doi.org/10.1007/978-981-10-1023-1_3

Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology. / Joshi, Vinod Kumar; Lobo, Haniel Craig.

Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015. Vol. 452 Springer Verlag, 2016. p. 25-40 (Advances in Intelligent Systems and Computing; Vol. 452).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.

AB - Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.

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DO - 10.1007/978-981-10-1023-1_3

M3 - Conference contribution

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VL - 452

T3 - Advances in Intelligent Systems and Computing

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BT - Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015

PB - Springer Verlag

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Joshi VK, Lobo HC. Comparative study of 7T, 8T, 9T and 10T SRAM with conventional 6T SRAM cell using 180 nm technology. In Advanced Computing and Communication Technologies - Proceedings of the 9th ICACCT, 2015. Vol. 452. Springer Verlag. 2016. p. 25-40. (Advances in Intelligent Systems and Computing). https://doi.org/10.1007/978-981-10-1023-1_3