Data stability and power consumption have been reported two important issues with scaling of CMOS technology. In this paper, we have revisited these issues on 6T, 7T, 8T, 9T, 10T SRAM cells individually and a comparative analysis has been done based on different parameters like read delay, write delay, power consumption and static noise margin (SNM). The read/write delay and power consumption has been found 0.671/0.267 ns, 1.69 μW for 6T SRAM cell, 0.456/0.752 ns, 1.09 μW for 7T SRAM cell, 0.517/0.392 ns, 1.82 μW for 8T SRAM cell, 0.388/0.181 ns, 1.3 μW for 9T SRAM cell and 0.167/0.242 ns, 2.01 μW for 10T SRAM cell respectively. SNM has been calculated 0.4 V for 6T SRAM cell, 0.375 V for 7T SRAM cell, 0.65 V for 8T SRAM cell, 0.65 V for 9T SRAM cell and 0.6 V for 10T SRAM cell. All the circuit of SRAM cells and their layout has been designed using Cadence virtuoso ADE tool and Cadence virtuoso layout suite respectively using 180 nm CMOS technology. The post layout simulation results have been shown a good agreement with pre layout simulation results.