Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology

Alan Saldanha, Vijil Gupta, Vinod Kumar Joshi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity. We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88%, 2.7% and 3.55% for CP1, CP3 and CP4, respectively, while it is 6.96% for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 µW power using 200 µA current source, CP3 consumes 1840 µW using 100 µA current source, CP1 consumes 704 µW using 80 µA current source, while CP2 consumes 756 µW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.

Original languageEnglish
Title of host publicationSoft Computing and Signal Processing - Proceedings of ICSCSP 2018
EditorsV. Kamakshi Prasad, G. Ram Mohana Reddy, Jiacun Wang, V. Sivakumar Reddy
PublisherSpringer Verlag
Pages683-692
Number of pages10
ISBN (Print)9789811335990
DOIs
Publication statusPublished - 01-01-2019
EventInternational Conference on Soft Computing and Signal Processing, ICSCSP 2018 - Hyderabad, India
Duration: 22-06-201823-06-2018

Publication series

NameAdvances in Intelligent Systems and Computing
Volume900
ISSN (Print)2194-5357

Conference

ConferenceInternational Conference on Soft Computing and Signal Processing, ICSCSP 2018
CountryIndia
CityHyderabad
Period22-06-1823-06-18

Fingerprint

Voltage control
Pumps
Electric potential
Phase locked loops
Bias voltage
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Computer Science(all)

Cite this

Saldanha, A., Gupta, V., & Joshi, V. K. (2019). Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology. In V. K. Prasad, G. R. M. Reddy, J. Wang, & V. S. Reddy (Eds.), Soft Computing and Signal Processing - Proceedings of ICSCSP 2018 (pp. 683-692). (Advances in Intelligent Systems and Computing; Vol. 900). Springer Verlag. https://doi.org/10.1007/978-981-13-3600-3_65
Saldanha, Alan ; Gupta, Vijil ; Joshi, Vinod Kumar. / Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology. Soft Computing and Signal Processing - Proceedings of ICSCSP 2018. editor / V. Kamakshi Prasad ; G. Ram Mohana Reddy ; Jiacun Wang ; V. Sivakumar Reddy. Springer Verlag, 2019. pp. 683-692 (Advances in Intelligent Systems and Computing).
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abstract = "We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity. We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88{\%}, 2.7{\%} and 3.55{\%} for CP1, CP3 and CP4, respectively, while it is 6.96{\%} for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 µW power using 200 µA current source, CP3 consumes 1840 µW using 100 µA current source, CP1 consumes 704 µW using 80 µA current source, while CP2 consumes 756 µW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.",
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Saldanha, A, Gupta, V & Joshi, VK 2019, Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology. in VK Prasad, GRM Reddy, J Wang & VS Reddy (eds), Soft Computing and Signal Processing - Proceedings of ICSCSP 2018. Advances in Intelligent Systems and Computing, vol. 900, Springer Verlag, pp. 683-692, International Conference on Soft Computing and Signal Processing, ICSCSP 2018, Hyderabad, India, 22-06-18. https://doi.org/10.1007/978-981-13-3600-3_65

Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology. / Saldanha, Alan; Gupta, Vijil; Joshi, Vinod Kumar.

Soft Computing and Signal Processing - Proceedings of ICSCSP 2018. ed. / V. Kamakshi Prasad; G. Ram Mohana Reddy; Jiacun Wang; V. Sivakumar Reddy. Springer Verlag, 2019. p. 683-692 (Advances in Intelligent Systems and Computing; Vol. 900).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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N2 - We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity. We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88%, 2.7% and 3.55% for CP1, CP3 and CP4, respectively, while it is 6.96% for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 µW power using 200 µA current source, CP3 consumes 1840 µW using 100 µA current source, CP1 consumes 704 µW using 80 µA current source, while CP2 consumes 756 µW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.

AB - We have reinvestigated the four different charge pumps (CPs) already reported in the literature and named them CP1, CP2, CP3 and CP4. These charge pumps are widely used in phase-locked loop (PLL) and have been compared for a number of parameters, mainly current mismatch, power consumption, voltage swing and the design complexity. We observed the current mismatch between the charging and discharging currents at control voltage of 0.9 V to be 3.88%, 2.7% and 3.55% for CP1, CP3 and CP4, respectively, while it is 6.96% for CP2 at control voltage of 1.3 V. At frequency of 50 MHz, CP4 consumes 377 µW power using 200 µA current source, CP3 consumes 1840 µW using 100 µA current source, CP1 consumes 704 µW using 80 µA current source, while CP2 consumes 756 µW power for bias voltage of 0.47 V. The voltage swing for CP1, CP2, CP3 and CP4 is obtained to be 0.2, 1.275, 0.9 and 0.3 V, respectively, at 50 MHz frequency.

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M3 - Conference contribution

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BT - Soft Computing and Signal Processing - Proceedings of ICSCSP 2018

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PB - Springer Verlag

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Saldanha A, Gupta V, Joshi VK. Comparison of low current mismatch CMOS charge pumps for analog PLLS using 180 nm technology. In Prasad VK, Reddy GRM, Wang J, Reddy VS, editors, Soft Computing and Signal Processing - Proceedings of ICSCSP 2018. Springer Verlag. 2019. p. 683-692. (Advances in Intelligent Systems and Computing). https://doi.org/10.1007/978-981-13-3600-3_65