Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies

Anand Ilakal, Anuj Grover

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.

Original languageEnglish
Title of host publicationVLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers
PublisherSpringer Verlag
Pages414-420
Number of pages7
ISBN (Print)9789811074691
DOIs
Publication statusPublished - 01-01-2017
Externally publishedYes
Event21st International Symposium on VLSI Design and Test, VDAT 2017 - Roorkee, India
Duration: 29-06-201702-07-2017

Publication series

NameCommunications in Computer and Information Science
Volume711
ISSN (Print)1865-0929

Conference

Conference21st International Symposium on VLSI Design and Test, VDAT 2017
CountryIndia
CityRoorkee
Period29-06-1702-07-17

Fingerprint

Soft Error
Static random access storage
Error Rate
Layout
Topology
Robustness
Data storage equipment
Cell
Estimate
Alpha particles
Cosmic rays
Energy transfer
Cosmic Rays
Neutrons
Energy Transfer
T-cells
Simulators
Neutron
High Energy
Radiation

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Mathematics(all)

Cite this

Ilakal, A., & Grover, A. (2017). Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. In VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers (pp. 414-420). (Communications in Computer and Information Science; Vol. 711). Springer Verlag. https://doi.org/10.1007/978-981-10-7470-7_41
Ilakal, Anand ; Grover, Anuj. / Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. Springer Verlag, 2017. pp. 414-420 (Communications in Computer and Information Science).
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abstract = "The impact of high energy particles in digital memory elements becomes important as technology scales down. The memory elements hold high density latches to store data and these latches are susceptible to disturbs due to particle strikes. The alpha particles, neutrons from cosmic rays may cause Single Event Upset (SEU) in memory cells. In this paper, we propose a method to estimate and compare SER robustness of different layout topologies of SRAM cell. We demonstrate that the radiation hardened layout topologies offer much better Soft Error Rate (SER) robustness compared to conventional layout of the 6-T SRAM cell in 28FDSOI and 40nm technology. The analysis is done using ELDO simulator for a wide range of Linear Energy Transfer (LET) profiles of particle strikes.",
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Ilakal, A & Grover, A 2017, Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. in VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. Communications in Computer and Information Science, vol. 711, Springer Verlag, pp. 414-420, 21st International Symposium on VLSI Design and Test, VDAT 2017, Roorkee, India, 29-06-17. https://doi.org/10.1007/978-981-10-7470-7_41

Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. / Ilakal, Anand; Grover, Anuj.

VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. Springer Verlag, 2017. p. 414-420 (Communications in Computer and Information Science; Vol. 711).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Ilakal A, Grover A. Comparison of SRAM cell layout topologies to estimate improvement in SER robustness in 28FDSOI and 40 nm technologies. In VLSI Design and Test - 21st International Symposium, VDAT 2017, Revised Selected Papers. Springer Verlag. 2017. p. 414-420. (Communications in Computer and Information Science). https://doi.org/10.1007/978-981-10-7470-7_41