Design and implementation of high-performance hybridadders

The paper presents a comparative study of hybrid adders which support in reducing the computational delay. In any digital system such as MAC unit, adder is a basic building block and its speed of operation is an important factor for high performance. With emphasis on reducing delay, w e proposed designs of two types of hybrid adders in which onetype has both Carry save and Carry skip adders and another type has the same adder combination as that of the previous one but with full adder replaced with a reversible logic gate. The delay values of both designs are compared. The delay ofhybrid adder using a reversible logic gate is 30% less when compared to the hybrid adder without reversible logic gate. This design is implemented, simulated, evaluated using Xilinx ISE tool and the target device used is Xilinx Spartan 3E XC3S500E.