Design of framework for logic synthesis engine

Tribikram Pradhan, Pramod Kumar, N. S. Anil, Amit Bakshi

Research output: Contribution to journalArticle

Abstract

Logic synthesis is a novel architectural concept used for converting a high level description of logic circuit into optimized gate level description. The method ranges from transforming a RTL description to producing an optimized netlist. Logic minimization plays an important role in optimization of logic synthesis. This optimization is done through the function minimization through different existing methods. The existing work on function minimization has resulted into many algorithms. In the proposed work, we form the basis for our synthesis engines vide detailed performance analysis and insight into the various minimization algorithms proposed erstwhile, and apply them on some real example circuit. We plan to propose our own algorithm as well for enhanced performance.

Original languageEnglish
Pages (from-to)1710-1715
Number of pages6
JournalInternational Journal of Engineering and Technology
Volume5
Issue number2
Publication statusPublished - 2013

Fingerprint

Engines
Logic circuits
Logic Synthesis
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Pradhan, T., Kumar, P., Anil, N. S., & Bakshi, A. (2013). Design of framework for logic synthesis engine. International Journal of Engineering and Technology, 5(2), 1710-1715.
Pradhan, Tribikram ; Kumar, Pramod ; Anil, N. S. ; Bakshi, Amit. / Design of framework for logic synthesis engine. In: International Journal of Engineering and Technology. 2013 ; Vol. 5, No. 2. pp. 1710-1715.
@article{784f0a80588c47e9800d8defa1152181,
title = "Design of framework for logic synthesis engine",
abstract = "Logic synthesis is a novel architectural concept used for converting a high level description of logic circuit into optimized gate level description. The method ranges from transforming a RTL description to producing an optimized netlist. Logic minimization plays an important role in optimization of logic synthesis. This optimization is done through the function minimization through different existing methods. The existing work on function minimization has resulted into many algorithms. In the proposed work, we form the basis for our synthesis engines vide detailed performance analysis and insight into the various minimization algorithms proposed erstwhile, and apply them on some real example circuit. We plan to propose our own algorithm as well for enhanced performance.",
author = "Tribikram Pradhan and Pramod Kumar and Anil, {N. S.} and Amit Bakshi",
year = "2013",
language = "English",
volume = "5",
pages = "1710--1715",
journal = "International Journal of Engineering and Technology",
issn = "2319-8613",
publisher = "Engg Journals Publications",
number = "2",

}

Pradhan, T, Kumar, P, Anil, NS & Bakshi, A 2013, 'Design of framework for logic synthesis engine', International Journal of Engineering and Technology, vol. 5, no. 2, pp. 1710-1715.

Design of framework for logic synthesis engine. / Pradhan, Tribikram; Kumar, Pramod; Anil, N. S.; Bakshi, Amit.

In: International Journal of Engineering and Technology, Vol. 5, No. 2, 2013, p. 1710-1715.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Design of framework for logic synthesis engine

AU - Pradhan, Tribikram

AU - Kumar, Pramod

AU - Anil, N. S.

AU - Bakshi, Amit

PY - 2013

Y1 - 2013

N2 - Logic synthesis is a novel architectural concept used for converting a high level description of logic circuit into optimized gate level description. The method ranges from transforming a RTL description to producing an optimized netlist. Logic minimization plays an important role in optimization of logic synthesis. This optimization is done through the function minimization through different existing methods. The existing work on function minimization has resulted into many algorithms. In the proposed work, we form the basis for our synthesis engines vide detailed performance analysis and insight into the various minimization algorithms proposed erstwhile, and apply them on some real example circuit. We plan to propose our own algorithm as well for enhanced performance.

AB - Logic synthesis is a novel architectural concept used for converting a high level description of logic circuit into optimized gate level description. The method ranges from transforming a RTL description to producing an optimized netlist. Logic minimization plays an important role in optimization of logic synthesis. This optimization is done through the function minimization through different existing methods. The existing work on function minimization has resulted into many algorithms. In the proposed work, we form the basis for our synthesis engines vide detailed performance analysis and insight into the various minimization algorithms proposed erstwhile, and apply them on some real example circuit. We plan to propose our own algorithm as well for enhanced performance.

UR - http://www.scopus.com/inward/record.url?scp=84878412235&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84878412235&partnerID=8YFLogxK

M3 - Article

VL - 5

SP - 1710

EP - 1715

JO - International Journal of Engineering and Technology

JF - International Journal of Engineering and Technology

SN - 2319-8613

IS - 2

ER -