Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics

G. S. Sai Venkatramana Prasada, G. Seshikala, S. Niranjana

Research output: Contribution to journalArticle

Abstract

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

Original languageEnglish
Pages (from-to)1064-1067
Number of pages4
JournalInternational Journal of Recent Technology and Engineering
Volume8
Issue number2 Special issue 3
DOIs
Publication statusPublished - 01-07-2019
Externally publishedYes

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Computer hardware description languages
Multiplier
Floating
Mathematics

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Management of Technology and Innovation

Cite this

Sai Venkatramana Prasada, G. S. ; Seshikala, G. ; Niranjana, S. / Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics. In: International Journal of Recent Technology and Engineering. 2019 ; Vol. 8, No. 2 Special issue 3. pp. 1064-1067.
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Design of high speed 32-bit floating point multiplier using Urdhva Triyagbhyam sutra of vedic mathematics. / Sai Venkatramana Prasada, G. S.; Seshikala, G.; Niranjana, S.

In: International Journal of Recent Technology and Engineering, Vol. 8, No. 2 Special issue 3, 01.07.2019, p. 1064-1067.

Research output: Contribution to journalArticle

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