Design of high speed carry select adder using modified parallel prefix adder

Abhishek R. Hebbar, Piyush Srivastava, Vinod Kumar Joshi

Research output: Contribution to journalConference article

Abstract

We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess - 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent - Kung (BK), Ladner - Fischer (LF) and Kogge - Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.

Original languageEnglish
Pages (from-to)317-324
Number of pages8
JournalProcedia Computer Science
Volume143
DOIs
Publication statusPublished - 01-01-2018
Event8th International Conference on Advances in Computing and Communications, ICACC 2018 - Kochi, India
Duration: 13-09-201815-09-2018

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Adders
Computer hardware description languages
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

Hebbar, Abhishek R. ; Srivastava, Piyush ; Joshi, Vinod Kumar. / Design of high speed carry select adder using modified parallel prefix adder. In: Procedia Computer Science. 2018 ; Vol. 143. pp. 317-324.
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Design of high speed carry select adder using modified parallel prefix adder. / Hebbar, Abhishek R.; Srivastava, Piyush; Joshi, Vinod Kumar.

In: Procedia Computer Science, Vol. 143, 01.01.2018, p. 317-324.

Research output: Contribution to journalConference article

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