We have proposed a modified Carry Select Adder (CSLA) structure which uses a parallel prefix structure with Binary to Excess - 1 converter (BEC). The proposed adder has been compared with Conventional, BEC, Brent - Kung (BK), Ladner - Fischer (LF) and Kogge - Stone (KS) based CSLA in terms of area, power consumption and performance. The proposed CSLA shows a significant decrease in the area and power compared to KS based CSLA. Particularly, the proposed CSLA structure exhibit significant improvement in speed by 54.41%, 7.95%, 7.82% to Conventional CSLA, 65.75%, 24.65%, 21.61% to BEC-CSLA, 50.79%, 13.83%, 9.30% to BK-CSLA, 43.12%, 8.99%, 5.35% to LF-CSLA, 44.64%, 10.50%, 6.30% to KS-CSLA for 4 bit, 8 bit and 16 bit respectively. All the CSLA structures are designed using Verilog HDL, simulations and synthesis have been performed in Cadence tool using 0.18 µm CMOS technology.
|Number of pages||8|
|Journal||Procedia Computer Science|
|Publication status||Published - 01-01-2018|
|Event||8th International Conference on Advances in Computing and Communications, ICACC 2018 - Kochi, India|
Duration: 13-09-2018 → 15-09-2018
All Science Journal Classification (ASJC) codes
- Computer Science(all)