Design of high-speed multiplier architecture based on vedic mathematics

High speed and efficient multipliers are essential components in today's computational circuits like digital signal processing, algorithms for cryptography and high performance processors. Invariably, almost all processing units will contain hardware multipliers based on some algorithm that fits the application requirement. Tremendous advances in VLSI technology over the past several years resulted in an increased need for high speed multipliers and compelled the designers to go for trade-offs among speed, power consumption and area. Amongst various methods of multiplication, Vedic multipliers are gaining ground due to their expected improvement in performance. A novel multiplier design for high speed VLSI applications using Urdhva-Tiryagbhyamsutra of Vedic Multiplication has been presented in this paper. The multiplier architecture is implemented using Verilog coding and synthesise during Cadence RTL Compiler. Physical design is implemented using Cadence Encounter RTL-to-GDSII System using standard 180nm technology. The proposed multiplier architecture is compared with the conventional multiplier and the results show significant improvement in speed and power dissipation.