TY - GEN
T1 - Design of multipliers for moduli 24k+22k+1-23k+1-2k+1and (24k-23k+1+2k-1
AU - Phalguna, P. S.
AU - Kamath, Dattaguru V.
AU - Mohan, P. V.Ananda
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021
Y1 - 2021
N2 - In this paper, the design of modulo multipliers for the moduli (24k+22k+1 -23k+1-2k+1and (24k-23k+1+2k-1 is investigated. These moduli are useful for constructing four moduli sets with interesting properties resulting in simpler RNS to binary conversion architectures. The derived architectures of the multipliers can facilitate binary to RNS conversion as well. Hardware requirements and multiplication time are derived in tems of basic gates and ASIC implementation results are presented.
AB - In this paper, the design of modulo multipliers for the moduli (24k+22k+1 -23k+1-2k+1and (24k-23k+1+2k-1 is investigated. These moduli are useful for constructing four moduli sets with interesting properties resulting in simpler RNS to binary conversion architectures. The derived architectures of the multipliers can facilitate binary to RNS conversion as well. Hardware requirements and multiplication time are derived in tems of basic gates and ASIC implementation results are presented.
UR - http://www.scopus.com/inward/record.url?scp=85126835414&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85126835414&partnerID=8YFLogxK
U2 - 10.1109/CCUBE53681.2021.9702727
DO - 10.1109/CCUBE53681.2021.9702727
M3 - Conference contribution
AN - SCOPUS:85126835414
T3 - 2021 International Conference on Circuits, Controls and Communications, CCUBE 2021
BT - 2021 International Conference on Circuits, Controls and Communications, CCUBE 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2021 International Conference on Circuits, Controls and Communications, CCUBE 2021
Y2 - 23 December 2021 through 24 December 2021
ER -