Efficient shift-add multiplier design using parallel prefix adder

Rohan Pinto, Kumara Shama

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

The overall performance of any DSP system depends on the performance of the arithmetic unit. Multiplication is one of the pivotal operation in it. The speed and area of the multiplier is always a matter of concern for the better performance of any processor. In this paper a simple and efficient multiplier for 8-bit and 16-bit have been proposed. The proposed structure is a modified version of Bypass Zero, Feed A Directly (BZ-FAD) multiplier. It has been implemented on FPGA, Spartan 6 device. This structure has low power and area because of its uniqueness in using the proposed parallel prefix structure for addition of partial products in multiplier. The proposed multiplier lowers the switching activity by 55% and area by 64%.

Original languageEnglish
Pages (from-to)45-53
Number of pages9
JournalInternational Journal of Control Theory and Applications
Volume9
Issue number39
Publication statusPublished - 2016

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Adders
Field programmable gate arrays (FPGA)

All Science Journal Classification (ASJC) codes

  • Computer Science(all)

Cite this

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Efficient shift-add multiplier design using parallel prefix adder. / Pinto, Rohan; Shama, Kumara.

In: International Journal of Control Theory and Applications, Vol. 9, No. 39, 2016, p. 45-53.

Research output: Contribution to journalArticle

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