Energy recovery flip-flops and resonant clocking of sccer flip-flop in H-tree clock network

Vinod Kumar Joshi

Research output: Contribution to journalArticle

Abstract

This paper indicates the four novel low power flip-flops collectively called novel energy recovery flipflops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the clock network, resulting in significant energy saving. The designed flip-flop operates with a single phase sinusoidal clock generated by an efficient power clock generator. A multiplier of 2 × 2 bit pipelined in 3 stages is designed. The schematic of the synthesized net list is generated and simulation results are presented for general D flip-flop and after replacing them by the designed SCCER flip-flop. The results show 43.56 % less power dissipation in compare to normal D flip-flop. In order to demonstrate the feasibility of energy recovery clocking, we integrated 64 energy recovery SCCER clocked flip-flops distributed across an area of 1 mm × 1 mm and clocked them by a single-phase sinusoidal clock through an 4 levels deep H-tree clock network. We report here that in H tree based clock network there is 90% of energy recovery for SCCER flip-flop over conventional flip-flop (HLFF).

Original languageEnglish
Pages (from-to)251-260
Number of pages10
JournalJournal of Electrical Engineering
Volume14
Issue number2
Publication statusPublished - 2014

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Flip flop circuits
Clocks
Recovery
Energy dissipation
Schematic diagrams
Energy conservation

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "This paper indicates the four novel low power flip-flops collectively called novel energy recovery flipflops to reduce the power dissipation in a clock network. The energy recovery clocked flip-flops enable energy recovery from the clock network, resulting in significant energy saving. The designed flip-flop operates with a single phase sinusoidal clock generated by an efficient power clock generator. A multiplier of 2 × 2 bit pipelined in 3 stages is designed. The schematic of the synthesized net list is generated and simulation results are presented for general D flip-flop and after replacing them by the designed SCCER flip-flop. The results show 43.56 {\%} less power dissipation in compare to normal D flip-flop. In order to demonstrate the feasibility of energy recovery clocking, we integrated 64 energy recovery SCCER clocked flip-flops distributed across an area of 1 mm × 1 mm and clocked them by a single-phase sinusoidal clock through an 4 levels deep H-tree clock network. We report here that in H tree based clock network there is 90{\%} of energy recovery for SCCER flip-flop over conventional flip-flop (HLFF).",
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Energy recovery flip-flops and resonant clocking of sccer flip-flop in H-tree clock network. / Joshi, Vinod Kumar.

In: Journal of Electrical Engineering, Vol. 14, No. 2, 2014, p. 251-260.

Research output: Contribution to journalArticle

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