Fully non-volatile hybrid full adder based on SHE+STT-MTJ/CMOS LIM architecture

Emerging hybrid spin-Hall-effect-assisted+spin transfer torque-magnetic tunnel junction (SHE+STT-MTJ)/CMOS logic-in-memory (LIM) architecture is considered as the promising next-generation candidate for the future digital integrated circuits. It overcomes the limitations of von Neumann architecture such as memory wall and also rises in the standby mode energy consumption. There are several full adder (FA) circuits based on the LIM architecture, which are either fully nonvolatile (NV) or partially NV. As the main disadvantage, these circuits suffer from wastage of write energy during the MTJ writing process. Furthermore, the existing fully NVFA can be used only for approximate computing. Hence, in this article, we have proposed fully NVFA for exact computation with self-write-termination read-write (SWTRW) circuitry. In SWTRW circuitry, wastage of write energy is eliminated due to a continuous monitoring (CM) and self-write-termination (SWT) process which saves a significant amount of energy of 95.88%. With the adaption of an improved sense amplifier, the NVFA developed in this article saves energy of 88.1% during computation/reading compared with its conventional counterpart. To add on, writing and reading the energy delay product (EDP) are also reduced by 90.56% and 78.76%, respectively.