High level modeling of physical layer noise parameters using SystemC

Prem Kumar Lohani, K. Ranjani, R. Ravi Shankar, C. Sundaresan, C. V.S. Chaitanya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Systemverilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. Both languages interoperate through an intermediate layer of abstraction known as Transaction Level Models (TLMs). This paper develops Universal Verification Methodology (UVM) TLM environment for SV and SC communication in the system modeling.

Original languageEnglish
Title of host publication2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages344-347
Number of pages4
Volume2014-August
ISBN (Electronic)9781479946211
DOIs
Publication statusPublished - 09-01-2015
Event2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014 - Kuala Lumpur, Malaysia
Duration: 27-08-201429-08-2014

Conference

Conference2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014
CountryMalaysia
CityKuala Lumpur
Period27-08-1429-08-14

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All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Management of Technology and Innovation
  • Computer Science Applications

Cite this

Lohani, P. K., Ranjani, K., Shankar, R. R., Sundaresan, C., & Chaitanya, C. V. S. (2015). High level modeling of physical layer noise parameters using SystemC. In 2014 4th International Conference on Engineering Technology and Technopreneuship, ICE2T 2014 (Vol. 2014-August, pp. 344-347). [7006275] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICE2T.2014.7006275