Implementation of HDLC controller design using Verilog HDL

Armaan Hasan Nagpurwala, C. Sundaresan, C. V.S. Chaitanya

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    HDLC Protocol is used to send the data in the form of frames, a controller controls the flow of data in DATA LINK LAYER of OSI model. HDLC protocol is used to transmit frames in logic link layer of Data link Layer. HDLC frame consists of an 8 bit Flag bit as 01111110, followed by control bits, information bits, fcs bits (CRC), address bits and terminates with flag bit. It involves processing of data before transmission, termed as Zero Stuffing, which is a special feature of HDLC protocol. A FIFO is used to transmit the data in the order of First In First Out. When complete data is transmitted, FIFO generates empty signal and the transmission of fcs, control, information and address bits begins. In the receiver side, detection of flag bits marks the beginning of new frame and zero unstuffing of data is performed. The unstuffed data is stored in variable length memory. The architecture for HDLC protocol has been proposed in this paper. The proposed model is implemented and verified using Verilog HDL.

    Original languageEnglish
    Title of host publication2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages7-10
    Number of pages4
    ISBN (Electronic)9781479931774
    DOIs
    Publication statusPublished - 01-01-2013
    Event2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013 - Selangor, Malaysia
    Duration: 04-12-201305-12-2013

    Conference

    Conference2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013
    CountryMalaysia
    CitySelangor
    Period04-12-1305-12-13

    Fingerprint

    Computer hardware description languages
    Controllers
    Network protocols
    OSI model
    Data communication systems
    Data storage equipment

    All Science Journal Classification (ASJC) codes

    • Electrical and Electronic Engineering
    • Control and Systems Engineering

    Cite this

    Nagpurwala, A. H., Sundaresan, C., & Chaitanya, C. V. S. (2013). Implementation of HDLC controller design using Verilog HDL. In 2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013 (pp. 7-10). [6895033] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEESE.2013.6895033
    Nagpurwala, Armaan Hasan ; Sundaresan, C. ; Chaitanya, C. V.S. / Implementation of HDLC controller design using Verilog HDL. 2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013. Institute of Electrical and Electronics Engineers Inc., 2013. pp. 7-10
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    Nagpurwala, AH, Sundaresan, C & Chaitanya, CVS 2013, Implementation of HDLC controller design using Verilog HDL. in 2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013., 6895033, Institute of Electrical and Electronics Engineers Inc., pp. 7-10, 2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013, Selangor, Malaysia, 04-12-13. https://doi.org/10.1109/ICEESE.2013.6895033

    Implementation of HDLC controller design using Verilog HDL. / Nagpurwala, Armaan Hasan; Sundaresan, C.; Chaitanya, C. V.S.

    2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013. Institute of Electrical and Electronics Engineers Inc., 2013. p. 7-10 6895033.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

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    AB - HDLC Protocol is used to send the data in the form of frames, a controller controls the flow of data in DATA LINK LAYER of OSI model. HDLC protocol is used to transmit frames in logic link layer of Data link Layer. HDLC frame consists of an 8 bit Flag bit as 01111110, followed by control bits, information bits, fcs bits (CRC), address bits and terminates with flag bit. It involves processing of data before transmission, termed as Zero Stuffing, which is a special feature of HDLC protocol. A FIFO is used to transmit the data in the order of First In First Out. When complete data is transmitted, FIFO generates empty signal and the transmission of fcs, control, information and address bits begins. In the receiver side, detection of flag bits marks the beginning of new frame and zero unstuffing of data is performed. The unstuffed data is stored in variable length memory. The architecture for HDLC protocol has been proposed in this paper. The proposed model is implemented and verified using Verilog HDL.

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    Nagpurwala AH, Sundaresan C, Chaitanya CVS. Implementation of HDLC controller design using Verilog HDL. In 2013 International Conference on Electrical, Electronics and System Engineering, ICEESE 2013. Institute of Electrical and Electronics Engineers Inc. 2013. p. 7-10. 6895033 https://doi.org/10.1109/ICEESE.2013.6895033