Low-power modified shift-add multiplier design using parallel prefix adder

Rohan Pinto, Kumara Shama

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier "bypass zero feed multiplicand directly," based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

Original languageEnglish
Article number1950019
JournalJournal of Circuits, Systems and Computers
Volume28
Issue number2
DOIs
Publication statusPublished - 01-02-2019

Fingerprint

Adders
Digital signal processors
Energy dissipation

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

@article{7093f02c27764e5b807aa5add3157bd6,
title = "Low-power modified shift-add multiplier design using parallel prefix adder",
abstract = "Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier {"}bypass zero feed multiplicand directly,{"} based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35{\%} predominantly for a 32-bit multiplier.",
author = "Rohan Pinto and Kumara Shama",
year = "2019",
month = "2",
day = "1",
doi = "10.1142/S0218126619500191",
language = "English",
volume = "28",
journal = "Journal of Circuits, Systems and Computers",
issn = "0218-1266",
publisher = "World Scientific Publishing Co. Pte Ltd",
number = "2",

}

Low-power modified shift-add multiplier design using parallel prefix adder. / Pinto, Rohan; Shama, Kumara.

In: Journal of Circuits, Systems and Computers, Vol. 28, No. 2, 1950019, 01.02.2019.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Low-power modified shift-add multiplier design using parallel prefix adder

AU - Pinto, Rohan

AU - Shama, Kumara

PY - 2019/2/1

Y1 - 2019/2/1

N2 - Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier "bypass zero feed multiplicand directly," based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

AB - Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier "bypass zero feed multiplicand directly," based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.

UR - http://www.scopus.com/inward/record.url?scp=85046700656&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85046700656&partnerID=8YFLogxK

U2 - 10.1142/S0218126619500191

DO - 10.1142/S0218126619500191

M3 - Article

VL - 28

JO - Journal of Circuits, Systems and Computers

JF - Journal of Circuits, Systems and Computers

SN - 0218-1266

IS - 2

M1 - 1950019

ER -