Multipliers are the building blocks of every digital signal processor (DSP). The performance of any digital system is dependent on the adder design and to a large extent on the multiplier block. Area and power dissipation are the major considerations in a multiplier design due to its complexity. In this paper, an efficient multiplier "bypass zero feed multiplicand directly," based on shift-add multiplication, has been proposed for low-power application. As the shift-add multiplication is a repetitive process of addition, the implementation time of an adder is reduced by using the proposed parallel prefix adders designed based on revised Ling equations. The proposed 8-bit, 16-bit and 32-bit multipliers are implemented using 180-nm and 90-nm CMOS technologies. Simulation results reveal that the proposed multiplier is fast and lowers the power by 35% predominantly for a 32-bit multiplier.
|Journal||Journal of Circuits, Systems and Computers|
|Publication status||Published - 01-02-2019|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering