Mathematical modeling of binary adders for logic level and gate count

Addition plays an important role in many applications. A wide range of binary adders are available in the literature, but most of them do not give a critical information gate count. In this paper, we propose generic mathematical equations in terms of logical level and gate count of binary adders around which further improvements have been attempted. These generic mathematical equations aid architect or researcher to quickly estimate the delay, and area for a given design. Using these mathematical equations, a software can be developed to choose a right design for the given constraint.