Mathematical modeling of binary adders for logic level and gate count

C. Sundaresan, Somashekara Bhat, P. R. Venkateswaran

Research output: Contribution to journalArticlepeer-review

Abstract

Addition plays an important role in many applications. A wide range of binary adders are available in the literature, but most of them do not give a critical information gate count. In this paper, we propose generic mathematical equations in terms of logical level and gate count of binary adders around which further improvements have been attempted. These generic mathematical equations aid architect or researcher to quickly estimate the delay, and area for a given design. Using these mathematical equations, a software can be developed to choose a right design for the given constraint.

Original languageEnglish
Pages (from-to)905-916
Number of pages12
JournalJournal of Advanced Research in Dynamical and Control Systems
Volume2017
Issue numberSpecial Issue 15
Publication statusPublished - 01-12-2017

All Science Journal Classification (ASJC) codes

  • Computer Science(all)
  • Engineering(all)

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