Memory architecture design for nano satellites

Nikhil Gupta, Bhavya Shahi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes the memory architecture to improve the data transfer and storage in a small satellite. The main objective during the design stage of the architecture is to find a good balance between power consumption, cost, reliability and data processing capability. These variables directly impact each other, and it is important to achieve a suitable balance. For this, a low power flash memory is selected in conjunction with a faster static random access memory to improve the performance of the on-board computer on the satellite. In-built buffers of flash are suitably used to improve system performance. An extensive study of timing requirements to store data in memory is done. A comparison of performance at different voltage levels above the required minimum is done to get a balance between the required speed of programming the memory and power consumption. A highly modular and optimized algorithm is proposed for data transfer and storage which can be easily incorporated into a real time operating system. A method to further save the power is proposed by switching the flash memory to the power saving mode when its usage is not required.

Original languageEnglish
Title of host publication2016 IEEE Aerospace Conference, AERO 2016
PublisherIEEE Computer Society
Volume2016-June
ISBN (Electronic)9781467376761
DOIs
Publication statusPublished - 27-06-2016
Externally publishedYes
Event2016 IEEE Aerospace Conference, AERO 2016 - Big Sky, United States
Duration: 05-03-201612-03-2016

Conference

Conference2016 IEEE Aerospace Conference, AERO 2016
CountryUnited States
CityBig Sky
Period05-03-1612-03-16

Fingerprint

Memory architecture
Flash memory
Satellites
Data transfer
Data storage equipment
Electric power utilization
flash
data storage
Computer programming
Printed circuit boards
airborne/spaceborne computers
random access memory
programming
Electric potential
buffers
time measurement
Costs
costs
requirements
electric potential

All Science Journal Classification (ASJC) codes

  • Aerospace Engineering
  • Space and Planetary Science

Cite this

Gupta, N., & Shahi, B. (2016). Memory architecture design for nano satellites. In 2016 IEEE Aerospace Conference, AERO 2016 (Vol. 2016-June). [7500695] IEEE Computer Society. https://doi.org/10.1109/AERO.2016.7500695
Gupta, Nikhil ; Shahi, Bhavya. / Memory architecture design for nano satellites. 2016 IEEE Aerospace Conference, AERO 2016. Vol. 2016-June IEEE Computer Society, 2016.
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Gupta, N & Shahi, B 2016, Memory architecture design for nano satellites. in 2016 IEEE Aerospace Conference, AERO 2016. vol. 2016-June, 7500695, IEEE Computer Society, 2016 IEEE Aerospace Conference, AERO 2016, Big Sky, United States, 05-03-16. https://doi.org/10.1109/AERO.2016.7500695

Memory architecture design for nano satellites. / Gupta, Nikhil; Shahi, Bhavya.

2016 IEEE Aerospace Conference, AERO 2016. Vol. 2016-June IEEE Computer Society, 2016. 7500695.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Gupta N, Shahi B. Memory architecture design for nano satellites. In 2016 IEEE Aerospace Conference, AERO 2016. Vol. 2016-June. IEEE Computer Society. 2016. 7500695 https://doi.org/10.1109/AERO.2016.7500695