Novel method of digital clock frequency multiplication and division using floating point arithmetic

Sundaresan Chidambaram, Vishnu Satya Chaitanya

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Abstract

    A digital clock frequency multiplier, divisor using floating point arithmetic which generates the output clock with almost zero frequency error has been presented. The circuit has an unbounded multiplication and division factor range and low lock time. A low power mechanism has been incorporated to ensure that the overall power consumption of the circuit is less. The circuit has been designed in TSMC 65nm CMOS process for an input reference time of 0.01ns and has been verified with random multiplication factor values.

    Original languageEnglish
    Title of host publicationProceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
    Pages592-595
    Number of pages4
    DOIs
    Publication statusPublished - 20-05-2013
    Event4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013 - Bangkok, Thailand
    Duration: 29-01-201331-01-2013

    Conference

    Conference4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013
    CountryThailand
    CityBangkok
    Period29-01-1331-01-13

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    All Science Journal Classification (ASJC) codes

    • Artificial Intelligence
    • Software
    • Modelling and Simulation
    • Theoretical Computer Science

    Cite this

    Chidambaram, S., & Chaitanya, V. S. (2013). Novel method of digital clock frequency multiplication and division using floating point arithmetic. In Proceedings - 4th International Conference on Intelligent Systems, Modelling and Simulation, ISMS 2013 (pp. 592-595). [6498340] https://doi.org/10.1109/ISMS.2013.22