A low drop-out [LDO] voltage regulator with fast transient response which does not require a capacitor for proper operation is proposed in this paper. Recent cap-less LDOs do not use off chip capacitor but instead they use on chip capacitor which occupy a large area on the chip. In the proposed LDO, this on chip capacitor is also avoided. A novel secondary local feedback technique is introduced which helps to achieve a good transient response even in the absence of output capacitor. Further an error amplifier that does need compensation capacitor is selected to reduce the on chip area. Stability analysis shows that the proposed LDO is stable with a phase margin of 78◦. The proposed LDO is laid out using Cadence Virtuoso in 180 nm standard CMOS technology. Post layout simulation is carried out and LDO gives 6mV/V and 360µV/mA line and load regulation respectively. An undershoot of 120 mV is observed during the load transition from 0 mA to 50 mA in 1 µs transition time, however LDO is able to recover within 1.4 µs. Since capacitor is not required in any part of design, it occupies only 0.010824 mm2 area on the chip.
|Number of pages||7|
|Journal||International Journal of Electronics and Telecommunications|
|Publication status||Published - 01-01-2019|
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Electrical and Electronic Engineering