Abstract
In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is 'Multiplication'. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. This paper focuses on the comparison of the 64×64 bit multipliers based on the Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah sutras of Vedic mathematics. The proposed designs were implemented using Verilog code and simulated using Xilinx10.1 for parameters such as slices, number of 4 input LUT's and delay. Simulation was also done using Cadence simvision with 45nm technology. 64×64 bit multiplier designed using Urdhva Tiryakbyham sutra exhibits less combinational delay and power utilization. But device utilization in Nikhilam multiplication is less compared to Urdhva multiplication.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 28-31 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538653234 |
| DOIs | |
| Publication status | Published - 25-03-2019 |
| Event | 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Mangalore, India Duration: 13-08-2018 → 14-08-2018 |
Publication series
| Name | 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings |
|---|
Conference
| Conference | 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 |
|---|---|
| Country | India |
| City | Mangalore |
| Period | 13-08-18 → 14-08-18 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Computer Networks and Communications
- Artificial Intelligence
- Hardware and Architecture
Cite this
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Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras. / Sai Venkatramana Prasada, G. S.; Seshikala, G.; Sampathila, Niranjana.
2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 28-31 8674125 (2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras
AU - Sai Venkatramana Prasada, G. S.
AU - Seshikala, G.
AU - Sampathila, Niranjana
PY - 2019/3/25
Y1 - 2019/3/25
N2 - In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is 'Multiplication'. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. This paper focuses on the comparison of the 64×64 bit multipliers based on the Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah sutras of Vedic mathematics. The proposed designs were implemented using Verilog code and simulated using Xilinx10.1 for parameters such as slices, number of 4 input LUT's and delay. Simulation was also done using Cadence simvision with 45nm technology. 64×64 bit multiplier designed using Urdhva Tiryakbyham sutra exhibits less combinational delay and power utilization. But device utilization in Nikhilam multiplication is less compared to Urdhva multiplication.
AB - In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is 'Multiplication'. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. This paper focuses on the comparison of the 64×64 bit multipliers based on the Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah sutras of Vedic mathematics. The proposed designs were implemented using Verilog code and simulated using Xilinx10.1 for parameters such as slices, number of 4 input LUT's and delay. Simulation was also done using Cadence simvision with 45nm technology. 64×64 bit multiplier designed using Urdhva Tiryakbyham sutra exhibits less combinational delay and power utilization. But device utilization in Nikhilam multiplication is less compared to Urdhva multiplication.
UR - http://www.scopus.com/inward/record.url?scp=85064199245&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85064199245&partnerID=8YFLogxK
U2 - 10.1109/DISCOVER.2018.8674125
DO - 10.1109/DISCOVER.2018.8674125
M3 - Conference contribution
AN - SCOPUS:85064199245
T3 - 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings
SP - 28
EP - 31
BT - 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -