Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras

G. S. Sai Venkatramana Prasada, G. Seshikala, Niranjana Sampathila

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is 'Multiplication'. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. This paper focuses on the comparison of the 64×64 bit multipliers based on the Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah sutras of Vedic mathematics. The proposed designs were implemented using Verilog code and simulated using Xilinx10.1 for parameters such as slices, number of 4 input LUT's and delay. Simulation was also done using Cadence simvision with 45nm technology. 64×64 bit multiplier designed using Urdhva Tiryakbyham sutra exhibits less combinational delay and power utilization. But device utilization in Nikhilam multiplication is less compared to Urdhva multiplication.

Original languageEnglish
Title of host publication2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages28-31
Number of pages4
ISBN (Electronic)9781538653234
DOIs
Publication statusPublished - 25-03-2019
Event2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Mangalore, India
Duration: 13-08-201814-08-2018

Publication series

Name2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings

Conference

Conference2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018
CountryIndia
CityMangalore
Period13-08-1814-08-18

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Computer hardware description languages
Microprocessor chips
Electric power utilization

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Computer Networks and Communications
  • Artificial Intelligence
  • Hardware and Architecture

Cite this

Sai Venkatramana Prasada, G. S., Seshikala, G., & Sampathila, N. (2019). Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras. In 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings (pp. 28-31). [8674125] (2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DISCOVER.2018.8674125
Sai Venkatramana Prasada, G. S. ; Seshikala, G. ; Sampathila, Niranjana. / Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras. 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 28-31 (2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings).
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abstract = "In VLSI systems like microprocessors and application specific DSP architectures, the arithmetic operation which is extensively used is 'Multiplication'. The overall performance of most of the systems is determined by the multipliers. The power efficient, faster and low area multiplier design decides the performance of the system. This paper focuses on the comparison of the 64×64 bit multipliers based on the Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah sutras of Vedic mathematics. The proposed designs were implemented using Verilog code and simulated using Xilinx10.1 for parameters such as slices, number of 4 input LUT's and delay. Simulation was also done using Cadence simvision with 45nm technology. 64×64 bit multiplier designed using Urdhva Tiryakbyham sutra exhibits less combinational delay and power utilization. But device utilization in Nikhilam multiplication is less compared to Urdhva multiplication.",
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Sai Venkatramana Prasada, GS, Seshikala, G & Sampathila, N 2019, Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras. in 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings., 8674125, 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 28-31, 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018, Mangalore, India, 13-08-18. https://doi.org/10.1109/DISCOVER.2018.8674125

Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras. / Sai Venkatramana Prasada, G. S.; Seshikala, G.; Sampathila, Niranjana.

2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 28-31 8674125 (2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Sai Venkatramana Prasada GS, Seshikala G, Sampathila N. Performance Analysis of 64×64 bit Multiplier Designed Using Urdhva Tiryakbyham and Nikhilam Navatashcaramam Dashatah Sutras. In 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. p. 28-31. 8674125. (2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings). https://doi.org/10.1109/DISCOVER.2018.8674125