TY - GEN
T1 - Performance Evaluation of Fault-Tolerant Approximate Adder
AU - Mendez, Tanya
AU - Nayak, Subramanya G.
N1 - Funding Information:
ACKNOWLEDGMENT The authors express gratitude to the Manipal Institute of Technology, Manipal Academy of Higher Education, for allowing Dr. T.M.A Pai Fellowship to complete this research. The authors are also grateful to the Manipal Institute of Technology’s Department of Electronics and Communication Engineering for providing laboratory space.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - The main emphasis of fault-tolerant adders is to minimize the performance metrics area, power and delay. Error resilient applications like Image processing, multimedia, and Internet of Things (IoT) accept degradation in the results providing a wide range of prospects for approximate adder's optimization. Three designs of fault-tolerant adders Selector Based Fault-Tolerant Adder-I (SBFTA-I), Selector Based Fault- Tolerant Adder-II (SBFTA-II) and Optimized Fault-Tolerant Adder (OFTA) are proposed and implemented in this work with reduced switching activity and gate count. The proposed fault tolerant adders are further used in the design of 16-bit adders, where the upper 8-bits are realized using actual adders, and the lower 8 bits are implemented using the three proposed fault tolerant adder designs. The proposed fault-tolerant and existing approximate adders are synthesized in an electronic design automation (EDA) Tool using a 90 nm technology library. The proposed adder designs showed significantly improved performance metrics compared to the conventional techniques
AB - The main emphasis of fault-tolerant adders is to minimize the performance metrics area, power and delay. Error resilient applications like Image processing, multimedia, and Internet of Things (IoT) accept degradation in the results providing a wide range of prospects for approximate adder's optimization. Three designs of fault-tolerant adders Selector Based Fault-Tolerant Adder-I (SBFTA-I), Selector Based Fault- Tolerant Adder-II (SBFTA-II) and Optimized Fault-Tolerant Adder (OFTA) are proposed and implemented in this work with reduced switching activity and gate count. The proposed fault tolerant adders are further used in the design of 16-bit adders, where the upper 8-bits are realized using actual adders, and the lower 8 bits are implemented using the three proposed fault tolerant adder designs. The proposed fault-tolerant and existing approximate adders are synthesized in an electronic design automation (EDA) Tool using a 90 nm technology library. The proposed adder designs showed significantly improved performance metrics compared to the conventional techniques
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U2 - 10.1109/ICDCS54290.2022.9780792
DO - 10.1109/ICDCS54290.2022.9780792
M3 - Conference contribution
AN - SCOPUS:85132306458
T3 - ICDCS 2022 - 2022 6th International Conference on Devices, Circuits and Systems
SP - 1
EP - 5
BT - ICDCS 2022 - 2022 6th International Conference on Devices, Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 6th International Conference on Devices, Circuits and Systems, ICDCS 2022
Y2 - 21 April 2022 through 22 April 2022
ER -