Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation

Rashmi Samanth, C. V.S. Chaitanya, G. Subramanya Nayak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In present embedded processors power consumption is a critical issue. One of the most common functional units in any processor is the Arithmetic Logic Unit (ALU) which performs different arithmetic and logical operations. As the operations become more and more complex it requires more power for the execution. In this implementation, low power ALU is designed by taking advantage of the concepts of operand isolation and clock gating low power techniques. Operand isolation prevents the data inputs from being propagated to unused logic blocks. Clock gating technique supports existing synchronous circuits with some additional logics to prune the clock tree, thus disabling the parts of the circuitry that are not in use. To estimate the effectiveness of the proposed techniques, a set of data path benchmark circuits using Cadence standard 180nm technology. It shows 63.63% to 49% of reduction in power with the smallest area overhead.

Original languageEnglish
Title of host publication2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728137353
DOIs
Publication statusPublished - 08-2019
Event3rd IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019 - Manipal, India
Duration: 11-08-201912-08-2019

Publication series

Name2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019 - Proceedings

Conference

Conference3rd IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019
CountryIndia
CityManipal
Period11-08-1912-08-19

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Decision Sciences (miscellaneous)
  • Information Systems and Management
  • Electrical and Electronic Engineering
  • Computational Mathematics
  • Control and Optimization

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  • Cite this

    Samanth, R., Chaitanya, C. V. S., & Nayak, G. S. (2019). Power Reduction of a Functional unit using RT-Level Clock-Gating and Operand Isolation. In 2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019 - Proceedings [9008025] (2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2019 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DISCOVER47552.2019.9008025