### Abstract

Here i have reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an example f = b(a+c) and same is proved using MATLAB 7.10.0 (R2010a). I showed the advantage of Binary Decision Diagram (BDD) for computing the probability of given Boolean function. The effect of technology mapping is reviewed with an example f = ab + cd using the cost metric of minimum area and minimum power mapping. The area mapped circuit has less area than the power mapped circuit but it has 22% higher switched capacitance as reported in literature. I observed that the area mapped circuit has ≈ 28 % less area and power cost has also been reduced three times of power mapped circuit for the same circuit with probability P (a, b, c = 1) = 0.5. The reason for this effective change is the transition probability (P_{t}). I found that in minimum area mapping the lower transition probability (P_{t} = 0.058) point is driven by AOI22 library having high intrinsic and load capacitance while in minimum power mapping case the lower transition probability point is driven by a much lower capacitance of G3, a NAND2 gate. Beside that internal switching capacitance of G1 and G2 is included to make the power cost so high. I also showed that a tree structure consume more power than a chain structure with an example f = abcd, the same is used to show the effect of pin ordering on transition probabilities that directly affect the dynamic power.

Original language | English |
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Title of host publication | 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings |

Pages | 616-621 |

Number of pages | 6 |

DOIs | |

Publication status | Published - 2013 |

Event | 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Peradeniya, United States Duration: 17-12-2013 → 20-12-2013 |

### Conference

Conference | 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 |
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Country | United States |

City | Peradeniya |

Period | 17-12-13 → 20-12-13 |

### Fingerprint

### All Science Journal Classification (ASJC) codes

- Information Systems

### Cite this

*2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings*(pp. 616-621). [6732055] https://doi.org/10.1109/ICIInfS.2013.6732055

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*2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings.*, 6732055, pp. 616-621, 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013, Peradeniya, United States, 17-12-13. https://doi.org/10.1109/ICIInfS.2013.6732055

**Probabilistic power analysis technique for low power VLSI circuits.** / Joshi, Vinod Kumar.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Probabilistic power analysis technique for low power VLSI circuits

AU - Joshi, Vinod Kumar

PY - 2013

Y1 - 2013

N2 - Here i have reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an example f = b(a+c) and same is proved using MATLAB 7.10.0 (R2010a). I showed the advantage of Binary Decision Diagram (BDD) for computing the probability of given Boolean function. The effect of technology mapping is reviewed with an example f = ab + cd using the cost metric of minimum area and minimum power mapping. The area mapped circuit has less area than the power mapped circuit but it has 22% higher switched capacitance as reported in literature. I observed that the area mapped circuit has ≈ 28 % less area and power cost has also been reduced three times of power mapped circuit for the same circuit with probability P (a, b, c = 1) = 0.5. The reason for this effective change is the transition probability (Pt). I found that in minimum area mapping the lower transition probability (Pt = 0.058) point is driven by AOI22 library having high intrinsic and load capacitance while in minimum power mapping case the lower transition probability point is driven by a much lower capacitance of G3, a NAND2 gate. Beside that internal switching capacitance of G1 and G2 is included to make the power cost so high. I also showed that a tree structure consume more power than a chain structure with an example f = abcd, the same is used to show the effect of pin ordering on transition probabilities that directly affect the dynamic power.

AB - Here i have reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an example f = b(a+c) and same is proved using MATLAB 7.10.0 (R2010a). I showed the advantage of Binary Decision Diagram (BDD) for computing the probability of given Boolean function. The effect of technology mapping is reviewed with an example f = ab + cd using the cost metric of minimum area and minimum power mapping. The area mapped circuit has less area than the power mapped circuit but it has 22% higher switched capacitance as reported in literature. I observed that the area mapped circuit has ≈ 28 % less area and power cost has also been reduced three times of power mapped circuit for the same circuit with probability P (a, b, c = 1) = 0.5. The reason for this effective change is the transition probability (Pt). I found that in minimum area mapping the lower transition probability (Pt = 0.058) point is driven by AOI22 library having high intrinsic and load capacitance while in minimum power mapping case the lower transition probability point is driven by a much lower capacitance of G3, a NAND2 gate. Beside that internal switching capacitance of G1 and G2 is included to make the power cost so high. I also showed that a tree structure consume more power than a chain structure with an example f = abcd, the same is used to show the effect of pin ordering on transition probabilities that directly affect the dynamic power.

UR - http://www.scopus.com/inward/record.url?scp=84894464453&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84894464453&partnerID=8YFLogxK

U2 - 10.1109/ICIInfS.2013.6732055

DO - 10.1109/ICIInfS.2013.6732055

M3 - Conference contribution

AN - SCOPUS:84894464453

SN - 9781479909100

SP - 616

EP - 621

BT - 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings

ER -