Probabilistic power analysis technique for low power VLSI circuits

Vinod Kumar Joshi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Here i have reviewed the previous works in literature for low power at gate level logic transformation in synthesis process. I applied the probabilistic power analysis technique with an example f = b(a+c) and same is proved using MATLAB 7.10.0 (R2010a). I showed the advantage of Binary Decision Diagram (BDD) for computing the probability of given Boolean function. The effect of technology mapping is reviewed with an example f = ab + cd using the cost metric of minimum area and minimum power mapping. The area mapped circuit has less area than the power mapped circuit but it has 22% higher switched capacitance as reported in literature. I observed that the area mapped circuit has ≈ 28 % less area and power cost has also been reduced three times of power mapped circuit for the same circuit with probability P (a, b, c = 1) = 0.5. The reason for this effective change is the transition probability (Pt). I found that in minimum area mapping the lower transition probability (Pt = 0.058) point is driven by AOI22 library having high intrinsic and load capacitance while in minimum power mapping case the lower transition probability point is driven by a much lower capacitance of G3, a NAND2 gate. Beside that internal switching capacitance of G1 and G2 is included to make the power cost so high. I also showed that a tree structure consume more power than a chain structure with an example f = abcd, the same is used to show the effect of pin ordering on transition probabilities that directly affect the dynamic power.

Original languageEnglish
Title of host publication2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings
Pages616-621
Number of pages6
DOIs
Publication statusPublished - 2013
Event2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Peradeniya, United States
Duration: 17-12-201320-12-2013

Conference

Conference2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013
CountryUnited States
CityPeradeniya
Period17-12-1320-12-13

Fingerprint

VLSI circuits
Capacitance
Networks (circuits)
Binary decision diagrams
Costs
Boolean functions
MATLAB

All Science Journal Classification (ASJC) codes

  • Information Systems

Cite this

Joshi, V. K. (2013). Probabilistic power analysis technique for low power VLSI circuits. In 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings (pp. 616-621). [6732055] https://doi.org/10.1109/ICIInfS.2013.6732055
Joshi, Vinod Kumar. / Probabilistic power analysis technique for low power VLSI circuits. 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings. 2013. pp. 616-621
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Joshi, VK 2013, Probabilistic power analysis technique for low power VLSI circuits. in 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings., 6732055, pp. 616-621, 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013, Peradeniya, United States, 17-12-13. https://doi.org/10.1109/ICIInfS.2013.6732055

Probabilistic power analysis technique for low power VLSI circuits. / Joshi, Vinod Kumar.

2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings. 2013. p. 616-621 6732055.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Joshi VK. Probabilistic power analysis technique for low power VLSI circuits. In 2013 IEEE 8th International Conference on Industrial and Information Systems, ICIIS 2013 - Conference Proceedings. 2013. p. 616-621. 6732055 https://doi.org/10.1109/ICIInfS.2013.6732055